Wireless devices have been in use for many years for enabling mobile communication of voice and data. Such devices can include mobile phones and wireless enabled personal digital assistants (PDA's) for example. FIG. 1 is a generic block diagram of the core components of such wireless devices. The wireless core 10 includes a base band processor 12 for controlling application specific functions of the wireless device and for providing and receiving voice or data signals to a radio frequency (RF) transceiver chip 14. The RF transceiver chip 14 is responsible for frequency up-conversion of transmission signals, and frequency down-conversion of received signals. RF transceiver chip 14 includes a receiver core 16 connected to an antenna 18 for receiving transmitted signals from a base station or another mobile device, and a transmitter core 20 for transmitting signals through the antenna 18 via a gain circuit 22. Those of skill in the art should understand that FIG. 1 is a simplified block diagram, and can include other functional blocks that may be necessary to enable proper operation or functionality.
Generally, the transmitter core 20 is responsible for up-converting electromagnetic signals from base band to higher frequencies for transmission, while receiver core 16 is responsible for down-converting those high frequencies back to their original frequency band when they reach the receiver, processes known as up-conversion and down-conversion (or modulation and demodulation) respectively. The original (or base band) signal, may be, for example, data, voice or video. These base band signals may be produced by transducers such as microphones or video cameras, be computer generated, or transferred from an electronic storage device. In general, the high frequencies provide longer range and higher capacity channels than base band signals, and because high frequency radio frequency (RF) signals can propagate through the air, they are preferably used for wireless transmissions as well as hard-wired or fibre channels.
All of these signals are generally referred to as radio frequency (RF) signals, which are electromagnetic signals; that is, waveforms with electrical and magnetic properties within the electromagnetic spectrum normally associated with radio wave propagation.
The receiver core 16 can include a receiver path consisting of a low noise amplifier, one or more mixers, filters, an analog-to-digital converter and a variable gain amplifier. This listing of components in receiver core is not comprehensive, and any person of skill in the art will understand that the specific configuration will depend on the communication standard being adhered to and the chosen architecture implementation.
Several different receiver architectures are known, such as super-heterodyne, image rejection, direct conversion, near zero-IF conversion and harmonic mixing architectures. The direct conversion architecture performs RF to base band frequency translation in a single step. The RF signal is mixed with a local oscillator at the carrier frequency, therefore there is no image frequency, and no image components to corrupt the signal, which prove problematic for the other architectures.
An important component of the receiver path is the mixer circuit that is responsible for modulating (down converting or upconverting) an input RF signal to the base band frequency clock. Ideally, the mixer circuit is an ideal linear circuit, meaning that the relationship between the input of the circuit and the output of the circuit is linear.
An example of a known differential mixer circuit is shown in FIG. 2. Differential pair mixer circuit 40 is an active mixing circuit, which includes a load resistor R1 and n-channel transistor 42 connected in series between a voltage supply VCC and a drain terminal of input n-channel transistor 44, and a load resistor R2 and n-channel transistor 46 connected in series between VCC and the same drain terminal of input n-channel transistor 44. The gate terminal of n-channel transistor 42 receives the signal z, and the gate terminal of n-channel transistor 44 receives the complement of the signal z denoted as z*. The gate terminal of input n-channel transistor 44 receives RF input signal x, and its source terminal is connected to VSS. The resulting complementary output signals y and y* are taken from the drain terminals of n-channel transistors 42 and 46 respectively. One output path 48 of mixer circuit 40 is between the drain of input n-channel transistor 44 and the node y, while the other output path 50 is between the drain of input n-channel transistor 44 and the node y*.
A problem with this circuit lies in the non-linear nature of input transistor 44, which will generate an output y/y* having undesired intermodulation products. The current “I” through input transistor 44 can be expressed in equation (1) below:I=gm*Vx, where gm is the transconductance and Vx is the voltage of input signal x  (1)
However, since gm of transistor 44 is a non-linear, the actual current “I” will be expressed by equation (2):I=a1Vx+a2Vx2+a3Vx3+a4Vx4  (2)
where a1, a2, a3 and a4 are coefficients, and terms from a2 and on are considered nth order intermodulation products.
The effect of the intermodulation products can be seen in the output y(t) of the mixer circuit 40 downconverted to baseband by z(t), which has a large frequency component at the RF signal frequency. FIG. 3a shows an input signal, x(t) made up of two tones ω1 and ω2. FIG. 3b shows the signal z(t), having a frequency tone at ωz used to down convert the signal x(t). After down conversion, the tones ω1 and ω2 are displaced by ωz. FIG. 3c shows the displacement of ω1 and ω2 as ω1−ωz and ω2−ωz respectively. The tone ω1−ω2 is generated by the second order term in equation (2). This tone effectively degrades the SNR of the radio. Thus, to mitigate the effect of second order intermodulation products, the linear relationship is ideally maintained by ensuring that all coefficients other than a1 are zero, so that those terms will disappear.
However, because mixer circuit 40 is a differential-type circuit, the a2 coefficient should be inherently reduced to zero. Differential circuits such as the one shown in FIG. 2 generally have two complementary data paths that should inherently cancel out any distortion components that may be introduced in them. Generally, differential-type circuits will set all even order terms a2, a4, a6 etc.=0.
In practice however, the even order terms will cancel only if the two complementary data paths are identically matched. In mixer circuit 44 of FIG. 2 for example, the even order terms will cancel the characteristics of both resistors R1 and R2 are identical (ie. R1=R2), the electrical characteristics of both transistors 42 and 46 are identical, and the connections between transistor 44 to 42 and 44 to 46 are identical. In this situation can both data paths can be considered matching. Therefore the second order intermodulation products should be inherently cancelled out.
However, this situation is ideal, and in practice the two data paths 48 and 50 are not electrically identical to each other. Semiconductor circuit layout and/or slight process variations and/or anomalies across the chip can introduce mis-match between the two paths. With reference to FIG. 2, the two load resistors can have slightly different values, or transistors 42 and 46 can have slightly differing doping levels or dimension differences, or un-balanced parasitic capacitance on the connections between the transistors, are sufficient to cause mis-match in the paths. This mis-match can cause the second order intermodulation products to appear. The data path mismatch can be compensated for by trimming one or both load resistors, or by digitally switching in different valued resistors that are pre-formed on the chip. This is typically done during testing of the fabricated devices by detecting and measuring the amplitudes of the second order intermodulation products, and then selecting the appropriate resistor that minimizes the magnitude of the second order intermodulation products.
Another known scheme of minimizing second order intermodulation products is balancing, or matching, the complementary output paths of a mixer by directly adding or removing current from one of the paths. This is shown with reference to the differential mixer 60 shown in FIG. 4.
Differential mixer 60 of FIG. 4 is substantially similar to the differential pair mixer circuit 40 shown in FIG. 2, but is configured to be responsive to both phases of the input signal x (x and x*), whereas the circuit of FIG. 2 is only responsive to a single phase of input signal x. Differential mixer 60 is effectively two differential pair type mixer circuits merged together. The first differential pair circuit includes a shared load resistor R1, bipolar transistor 62, bipolar transistor 64, bipolar transistor 66, and shared load resistor R2. Shared load resistor R1 and bipolar transistor 62 are serially connected between VCC and the collector terminal of bipolar transistor 66. Shared load resistor R2 and bipolar transistor 64 are serially connected between VCC and the collector terminal of bipolar transistor 66. Bipolar transistor 66 has a base terminal for receiving input signal x* and an emitter connected to VSS. The base terminal of bipolar transistor 62 receives signal z while the base terminal of bipolar transistor 64 receives z*, the opposite phase of signal z. Output signal OUT is generated from the collector terminal of bipolar transistor 62.
The second differential pair circuit includes a shared load resistor R2, bipolar transistor 68, bipolar transistor 70, bipolar transistor 70, and shared load resistor R2. Shared load resistor R2 and bipolar transistor 70 are serially connected between VCC and the collector terminal of bipolar transistor 72. Shared load resistor R1 and bipolar transistor 68 are serially connected between VCC and the collector terminal of bipolar transistor 72. Bipolar transistor 72 has a base terminal for receiving input signal x, being the opposite phase of x*, and an emitter connected to VSS. The base terminal of bipolar transistor 70 receives signal z while the base terminal of bipolar transistor 68 receives z*. Output signal OUT* is generated from the collector terminal of bipolar transistor 70.
The operation of differential mixer 60 is straightforward. When z is at a high voltage level, transistors 62 and 70 will be turned on, while transistors 64 and 68 are turned off. Conversely, when z* is at a high voltage level, transistors 64 and 68 will be turned on, while transistors 62 and 70 are turned off. Meanwhile, transistors 66 and 72 will turn on and off according to the level of input signal x/x*. Therefore, transistors 66 and 72 are alternately coupled to out and out* as signal z oscillates at a predetermined frequency. To correct for any mismatch in the output paths, a compensation circuit consisting of a programmable current source 74 can be connected between VCC and collector terminal of bipolar transistor 62. This current source can be digitally switched in from a bank of different current sources. Alternately, programmable current source 74 can be coupled to input node “r” in the circuit.
As previously shown in FIG. 4, the mixer circuit can be fabricated using bipolar technology, or SiGe, GaAs, and other heterojunction technologies. These technologies provide certain advantages for RF circuits, but are relatively new, very complex, and hence expensive. Consequently, the costs for manufacturing these RF devices can be prohibitive. Complementary Metal Oxide Semiconductor (CMOS) technology on the other hand, is a very mature and inexpensive fabrication process for the production of semiconductor devices.
Unfortunately, direct replacement of the bipolar transistors with CMOS transistors in the mixer circuits of FIG. 4 will add significant noise, which is undesirable. More specifically, since the transistors of the mixer circuits will constantly switch on and off, significant DC current will flow through them. This DC current will add significant amounts of noise, which will degrade the SNR of the receiver.
Even if the level of noise could be reduced to tolerable levels, the circuit path mismatch issues would still apply and may result in the generation of the second order intermodulation products. One solution is to ensure that the layout of the circuit paths are symmetrical and matched. However, potential CMOS transistor mismatch can contribute to circuit path mismatch even in a symmetrical circuit layout. This is primarily due to threshold voltage variations of the transistors. Tight transistor threshold voltage control is more easily obtained with larger sized transistors, however, larger sized transistors impose bandwidth limitations in addition to increased power consumption.
It is, therefore, desirable to provide a low cost, low noise CMOS mixer circuit with minimized even order intermodulation products caused by circuit path mismatch.